By Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins
With the earlier few decade efforts on lithography and integrated-circuit (IC) applied sciences, very reasonably cheap microsystems were effectively constructed for lots of various functions. the rage in instant communications is towards making a networkubiquitous period within the years yet to come. Many unparalleled possibilities and demanding situations, corresponding to layout for multi-standardability and low-voltage (LV) compliance, are swiftly changing into the mainstream instructions in wireless-IC study and improvement, on condition that the previous can supply the simplest connectivity between assorted networks, whereas the latter can facilitate the know-how migration into the sub-1-V nanoscale regimes for extra rate and tool aid.
Analog-Baseband Architecturees and Circuits presents architectural and circuit ideas for instant transceivers to accomplish multistandard and low-voltage compliance. the 1st a part of the booklet studies the actual layer requirements of contemporary instant verbal exchange criteria, offers the basic tradeoffs enthusiastic about transceiver structure choice, and gives case reports of the cutting-edge multistandard transceivers, the place the major ideas strengthened are highlighted and mentioned. A statistical precis (with a hundred+ references stated) of such a lot used transmitter and receiver architectures for contemporary communique criteria is equipped. all of the references are citied from the top boards, i.e., ISSCC, CICC, VLSI and ESSCIRC, from 1997 to 2005.
The moment half specializes in the architectural layout of multistandard transceivers. A coarse-RF fine-IF (two-step) channelselection strategy is disclosed. It, in the course of the reconfiguration of receiver and transmitter analog basebands, permits not just a leisure of the RF frequency synthesizer’s and native oscillator’s layout necessities, but in addition an effective multistandard compliance by way of synthesizing the low-IF and zero-IF within the receiver; and the direct-up and two-step-up within the transmitter. the primary is tested in few layout examples. considered one of them is a system-in-a-package (SiP) receiver analog baseband for IEEE 802.11a/b/g WLAN. It not just has the two-step channel choice embedded, but in addition incorporates a flexible-IF topology, a distinct 3D-stack floorplan, and a selected layout technique for top testability and routability.
The 3rd half offers with the circuit layout. as well as the methodical description of many LV circuit innovations, three tailormade LV-robust practical blocks are provided. They contain: 1) a double-quadrature-downconversion clear out (DQDF) – it realizes simultaneously clock-rate-defined IF reception, I/Q demodulation, IF channel choice and baseband filtering. 2) A switched-current-resistor (SCR) programmable-gain amplifier (PGA) – it bargains a transient-free constant-bandwidth achieve adjustment. three) An inside-OpAmp dc-offset canceler – it saves the silicon sector required for understanding a wide time consistent on chip whereas maximizing its highpass-pole switchability for quick dc-offset transient.
The final half provides experimental result of the three tailored construction blocks and a fully-integrated analog-baseband IC fabricated in a standard-VTH CMOS procedure. formerly untold on-/off-chip co-setup for either full-chip and development blocks measurements are defined. not just the construction blocks have effectively prolonged the state of the art boundary when it comes to sign bandwidth and provide voltage, the analog-baseband IC has been to date the lowest-voltage-reported resolution for IEEE 802.11a/b/g WLAN receivers.
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Additional resources for Analog-Baseband Architectures And Circuits For Multistandard And Lowvoltage Wireless Transceivers
Different from 14 Analog-Baseband Architectures and Circuits Case-III, the dc-offset cancellation for the PGA and LPF is relaxed in its highpass pole frequency. 5 Comparison of different receiver architectures Table 2-1 summarizes and compares the presented RX architectures. Their characteristics determine their appropriateness for use in modern wireless communication systems, as presented in Section 4. Table 2-1. Summary of different RX architectures RX Architecture Advantages Disadvantages Superheterodyne + Reliable performance + Flexible frequency plan + No DC offset and 1/f noise Image-Rejection (Hartley and Weaver) + Low cost + No DC offset and 1/f noise + High integratability – Expensive and bulky, high power – Difficult to share the SAW filters for multistandard – Quadrature RF-to-BB downconversion – Suffer from first and secondary images – Narrowband (Hartley) – High I/Q matching Zero-IF Low-IF 3.
Ahmed and D. Johns, “A 50MS/s (35mW) to 1kS/s (15µW) Power Scaleable 10b Pipelined ADC with Minimal Bias Current Variation,” IEEE International SolidState Circuits Conference (ISSCC), Digest of Technical Papers, pp. 280–281, Feb. 2005. B. Xia, A. Valdes-Garcia and E. Sánchez-Sinencio, “A Configurable TimeInterleaved Pipeline ADC for Multi-Standard Wireless Receivers,” in Proc. European Solid-State Circuits Conference (ESSCIRC), pp. 259–262, Sept. 2004. -I. -P. U and R. P. Martins, “Transceiver Architectural Selection: Review, State-of-the-Art Survey and Case Study,” IEEE Circuits and Systems Magazine, 2nd Issue, pp.
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