By Michiel Steyaert, Arthur van Roermund, Andrea Baschirotto
Analog Circuit layout includes the contribution of 18 tutorials of the twentieth workshop on Advances in Analog Circuit layout. every one half discusses a particular to-date subject on new and necessary layout rules within the region of analog circuit layout. each one half is gifted by way of six specialists in that box and state-of-the-art details is shared and overviewed. This ebook is quantity 20 during this winning sequence of Analog Circuit layout, offering invaluable info and perfect overviews of:
Topic 1 : Low Voltage Low strength, chairman: Andrea Baschirotto
Topic 2 : brief diversity instant Front-Ends, chairman: Arthur van Roermund
Topic three : strength administration and DC-DC, chairman : Michiel Steyaert.
Analog Circuit layout is a necessary reference resource for analog circuit designers and researchers wishing to maintain abreast with the most recent improvement within the box. the educational insurance additionally makes it compatible to be used in a complicated layout path.
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Additional resources for Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC
L. Sculley, A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter. IEEE J. Solid-State Circuits 37(6), 674–683 (2002) 30. , A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC. IEEE J. SolidState Circuits 38(12), 2031–2039 (2003) 31. K. Gulati, Lee Hae-Seung, A low-power reconfigurable analog-to-digital converter. IEEE J. Solid-State Circuits 36(12), 1900–1911 (2001) 32. C. 5 V 12 b 5 MSample/s pipelined CMOS ADC, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 1996, pp.
E. the output must not exceed the next quantizer’s full-scale range (VFS ). Assuming that the local sub-ADC is free of errors in its decision levels, this condition is ensured as long as G1 Ä 2B since the quantization error of a B-bit ADC is bounded by VFS /2B and thus G1 VFS /2B Ä VFS () G1 Ä 2B . The limit case of G1 D 2B with B D 2 is illustrated in Fig. 5. From this example, it is clear that any error in the sub-ADC decision levels will lead to over-ranging. Thus, it is impractical to design a stage for this limit case; it would require very high precision (and thus high power) in the sub-ADC comparators.
IEEE J. Solid-State Circuits 43(12), 2613–2619 (2008) 38. , A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter. IEEE J. Solid-State Circuits 23(6), 1324–1333 (1988) 2 Low-Power Pipelined A/D Conversion 37 39. M. R. 5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter, in Symposium of VLSI Circuits Digest, Honolulu, HI, USA, 1998, pp. 166–169 40. C. A. Hodges, Time interleaved converter arrays. IEEE J. Solid-State Circuits 15(6), 1022–1029 (1980) 41. K. , A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW power realized by a high bandwidth scalable time-interleaved architecture.